San Jose, CA(onsite) RESPONSIBILITIES: Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. Provide post-silicon testing and validation support Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems Run and debug non-timing and SDF annotated gate level simulations Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C+ BASIC QUALIFICATIONS: Bachelor's degree in electrical engineering, computer engineering or computer science 10+ years of experience in scan insertion and DFT setup, integration and validation PREFERRED SKILLS AND EXPERIENCE: Leadership experience driving SOC DFT execution from concept through tapeout and product deployment RTL experience to understand, trace and debug RTL connectivity issues as they pertain to DFT Ability to solve complex problems including clock domain crossings and power optimization Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience Strong implementation or integration of design blocks using Verilog/SystemVerilog Experience working with ATE testers and test teams