The Role

We are seeking a Senior Mixed-Signal Verification Engineer to own the creation of behavioral modeling and drive mixed-signal verification methodology from the ground up. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. Your work will directly influence top-level integration and silicon tapeout success. This is a high-impact, technical role with significant ownership across modeling, methodology, verification, and cross-functional alignment with RF, analog, and digital teams.

Responsibilities

• Develop high-level behavioral models for analog and mixed-signal IP (ADCs, DACs, PLLs, LDOs, RF front-end blocks, biasing, amplifiers, etc.).
• Create abstracted models using Verilog, Verilog-AMS, or SystemVerilog.
• Develop regression infrastructure and mixed-signal testbenches enabling co-simulation (digital + analog).
• Integrate AMS models into digital verification environments (UVM-based).
• Define and build the mixed-signal verification methodology for top-level SoC and subsystem verification.
• Support architectural exploration through early-phase modeling and system-level simulations.
• Collaborate with analog/RF designers to capture real-world analog behaviors and map them into accurate behavioral abstractions.
• Work with digital and verification teams to ensure seamless integration of AMS models.
• Provide modeling and verification insights during architectural reviews, PDR/CDR, and silicon bring-up.
• Act as technical leader and subject-matter expert.

Required Qualifications

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in analog/mixed-signal modeling and/or AMS verification.
• Hands-on experience with SystemVerilog, Verilog-AMS, wreal/RNM, or equivalent modeling languages.
• Strong understanding of analog/mixed-signal circuits (PLLs, LDOs, ADC/DACs, RF/IF paths, clocking, amplifiers).
• Experience with mixed-signal co-simulation environments (Cadence AMS Designer, Synopsys VCS AMS, or similar).

Preferred Qualifications

• Experience building AMS verification methodologies from scratch.
• Familiarity with UVM-based verification and digital design flows.
• Knowledge of signal processing theory, RF system modeling, or communication systems.
• Experience with MATLAB/Simulink, Python modeling, or SystemC AMS for high-level architectural modeling.
• Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

• Base salary range for this role is $160,000 – $230,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks