Responsibilities:

• You will contribute to a team that generates & verifies advanced analog circuit equivalent models to support analog design, UVM verification, & HW/SW validation platforms
• Collaborate with system architects and designers to streamline architectural exploration of next-generation IP
• Develop behavioral models using SystemVerilog Real Number Modeling (SV-RNM), User-defined Types(SV-UDT), & Verilog AMS
• Develop DMS & AMS test plans, test benches, and verification methodologies to verify microarchitectures
• Collaborate with multi-functional teams to streamline chip-level integration and maintain continuity of design, verification, and modeling feature drop plans
• Serve as a primary mixed signal design regression debug support
• Develop DMS & AMS test platforms and execute DMS & AMS test plans
• Contribute to analog design reviews and recommend enhancements for improved circuit design and partitioning
• Collaborate with UVM verification engineers to ensure all verification components are used for AMS-UVM flow
• Contribute to development of automation tools for design, verification and modeling

Required Skills and Qualifications:

• Master's degree or higher in Electrical Engineering or Computer Engineering
• Experience in development of mixed-signal products
• Strong background in analog integrated circuit design & proficient in interpreting circuit schematics
• Strong background in digital signal processing and control systems
• Strong background in System Verilog for real number modeling (RNM) modeling, test bench development & verification
• Organized and detailed with strong x-functional communication skills
• Possess outstanding analytical and problem-solving skills
• Proficient in use of AMS simulators

Preferred Skills and Qualifications:

• Teaming closely with digital/analog designers, applications engineers, and manufacturing test to support both pre-silicon verification and post-silicon validation efforts
• Knowledge of signal processing and System Verilog Assertions and PSL Assertions
• Experience with database management methodologies (Perforce, GIT, etc…)
• Working knowledge of UVM verification flows
• Working knowledge of Formal verification flows
• Simulink & Simscape
• Python scripting experience