What You'll Do

• Take ownership, lead, develop and maintain UVM-based and non-UVM-based verification environments for complex FPGA designs including cryptographic engines, protocol interfaces, and system-level integration testbenches
• Create comprehensive verification plans with functional coverage models, coverage goals, and closure criteria aligned to design specifications
• Implement constrained-random stimulus generators, monitors, scoreboards, and functional coverage collectors using SystemVerilog, VHDL and UVM
• Drive code coverage (statement, branch, condition, expression, toggle) and functional coverage to closure, analyzing coverage holes and developing targeted stimulus to fill gaps
• Develop and maintain automated simulation regression suites that run across multiple test configurations and random seeds
Build and improve CI/CD pipelines for automated verification workflows
• - including nightly regression runs, coverage trend tracking, and automated results reporting using Jenkins, GitLab CI, or similar platforms
• Perform assertion-based verification (ABV) using SystemVerilog Assertions (SVA) to capture protocol rules, interface contracts, and design invariants
• Debug complex design issues using waveform analysis (QuestaSim, Vivado), assertion failures, and coverage-driven investigation
• Collaborate closely with FPGA design engineers during architecture definition to ensure designs are verification-friendly and observable
• Review and contribute to design specifications, interface control documents, and verification closure reports
• Mentor junior verification engineers on UVM methodology, coverage-driven verification practices, and debugging techniques
• Support formal verification activities including property checking, connectivity verification, and equivalence checking where applicable

Required Qualifications

• Strong proficiency in SystemVerilog for verification, VHDL for verification including constrained-random stimulus, functional coverage, and assertions
• Hands-on experience with UVM (Universal Verification Methodology) including environment architecture, component development, and sequence libraries
• Experience with industry-standard simulation tools: QuestaSim/ModelSim Simulators
• Demonstrated ability to develop verification plans, define coverage models, and drive coverage to closure
• Experience with code coverage metrics (statement, branch, condition, expression, toggle) and coverage analysis workflows
• Proficiency in VHDL and/or Verilog for reading and understanding design RTL
• Experience with waveform debugging and signal-level analysis
• Understanding of AXI-Stream, AXI4, and similar on-chip bus protocols from a verification perspective
• Knowledge of clock domain crossing (CDC) verification concepts and metastability analysis
• Strong written and verbal communication skills for verification plans, coverage reports, and technical presentations
• S. Citizenship and ability to obtain/maintain a Secret security clearance

Preferred Qualifications

• Experience verifying cryptographic hardware implementations (AES, GCM, SHA, ECC, RSA, or similar)
Experience with CI/CD pipeline development and maintenance for FPGA verification (GitLab CI, GitHub Actions)
• - including automated regression management, seed management, and coverage merging
• Proficiency in scripting languages (Python, Tcl, Bash, Perl) for verification automation, log parsing, and results analysis
• Experience with Xilinx Vivado Design Suite and FPGA-specific verification challenges (timing simulation, post-synthesis/post-route verification)
• Knowledge of CDC analysis tools (Questa CDC) and lint/design rule checking tools
• Experience with emulation or prototyping platforms for hardware-in-the-loop verification
• Knowledge of AXI protocol specification and Questa verification IP (QVIP) usage for protocol compliance checking
• Experience with version control (Git), code review processes, and collaborative development workflows