Responsibilities

• Design and implement RTL modules using Verilog for DSP and data conversion ICs.
• Perform logic simulation, functional verification, and synthesis in a mixed-signal environment.
• Collaborate with the design team on integration and system-level verification.
• Support behavioral modeling of analog and mixed-signal circuits.
• Assist with test vector generation and lab test development.

Required Skills and Qualifications

• Currently pursuing a MS or PhD in Electrical Engineering or a related field.
• Strong understanding of Digital Signal Processing (DSP) concepts.
• Proficiency in Verilog and Synopsys-based design flows.
• Experience with Matlab for algorithm development and analysis.
• Familiarity with PWM techniques, transistor-level simulators, and place-and-route tools.