THE ROLE:

You will contribute to the ASIC (chip) design for high-performance network chips: AINIC and DPU. As a member of the NTSG ASIC Design Team, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.
THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• Network-on-Chip (NoC) design and integration
• AXI, ACE, and APB interface design and verification
• Queuing system design and implementation
• Collaboration with architecture, IP, and physical design teams for first-pass silicon success
• Post-silicon bring-up support and yield learning

PREFERRED EXPERIENCE:

• Understanding of Network-on-Chip (NoC) architecture, protocols, and design
• Experience with AXI, ACE, and APB interface design and verification
• Knowledge of queuing system design and buffer management
• Experience with VCS simulation tool, Perl/Python/Shell scripting, and SystemVerilog/Verilog RTL design

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering