Contribute to the definition of circuit architecture and to the design implementation of various state-of-the-art, low power blocks, and area efficient circuits for LPDDR PHY

Design circuits for High Speed IOs that include Transmitter, Receiver – CTLE/DFE, Delay Lines, DAC, OpAmp, Comparator and voltage regulators

Work closely with other teams to port design to different nodes while improving the overall PPA from previous generation

Develop models for link-level statistical performance simulation of the PHY (Link Training, PHY, DRAM, DB/RCD, DFE training, Transmit Equalization) and application of the same to the development and optimization of design.

Documentation of the micro-architecture and algorithms, and guidance of Analog, Digital, Firmware and Verification teams on the training and verification of the circuits.

Work closely with various disciplines, especially Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification to ensure optimal implementation of the overall PHY architecture and algorithms and full coverage of the features

Participate and contribute to the definition of development flows that improve efficiency and quality of execution

Lead design liaison for post Silicon characterization and productization/volume production efforts