Responsibilities

• Assist in verification planning and strategy development.
• Support testbench creation, maintenance, and enhancement.
• Contribute to failure analysis, debug, and resolution efforts.
• Help with coverage analysis and population to ensure thorough verification of mixed-signal products.
• Work on digital/mixed-signal modeling, directed and constraint-random test generation, and verification flow development.

Required Skills and Qualifications

• Currently pursuing a MS or PhD in Electrical Engineering or a related field.
• Strong background in Hardware Description Languages (HDLs) such as Verilog or VHDL.
• Familiarity with Hardware Verification Languages (HVLs) like SystemVerilog/UVM, Vera, or e.
• Solid understanding of digital design fundamentals and verification methodologies.