Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.…
Leading the design and implementation of next-generation STA algorithms addressing multi-billion-cell designs, advanced timing effects, and non-linear behaviors……
Collaborate with architecture, clocking design, DFT and logic design teams to develop flows for chip integration and validate clock network performance……
Work with design teams, DFT, CAD, and product engineering to design experiments, analyze results and refine design methodologies applied across all silicon……
Work with design teams, DFT, CAD, and product engineering to design experiments, analyze results and refine design methodologies applied across all silicon……
Expertise on circuit level analysis using tools like SPICE / SPECTRE. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible……
Expertise on circuit level analysis using tools like SPICE / SPECTRE. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible……
Experience with ASIC design flows and methodology of static timing analysis. Delivery of high-complexity silicon in state-of-the-art technology process nodes.…
Additionally, you will work with architecture, logic design, and Design for testing (DFT) teams to fully implement cross-functional design requirements.…
Provide timing closure guidance and mentorship to design and physical design engineers. Fluency with PrimeTime and related signoff tools (PT-SI, PTPX, PT-ECO),……
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Key Responsibilities:
Perform Synthesis, Equivalency Checking, and Static Timing Analysis (STA) for complex ASIC/SoC designs.
Drive Block-Level, Full-Chip (Top-Level), and Multi-Voltage Timing Closure.
Develop timing constraints, debug/fix timing issues, and support final timing signoff.
Work with CTS, timing exceptions, MMMC timing closure, and timing ECOs.
Automate STA tasks using Tcl/Perl scripting.
Required Skills:
Strong experience with Synopsys DC/FC, Formality, and PrimeTime.
Expertise in timing constraints, CTS, clock constraints, and ASIC design flow (RTL to P&R).
Experience with advanced technology nodes and hierarchical SoC designs.
Familiarity with Genus synthesis tool is a plus.
Bachelor's degree with 8+ years (or Master's with 6+ years) or PhD and 3+ years of related experience.
Pay: $100,000.00 - $150,000.00 per year
Work Location: In person
Base pay range
The minimum salary is $100K and the max salary is $150K.
$100K – $150K/yr (Employer provided)
$125K
/yr Median
San Jose, CA
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