first round is 1hr phone, speaking of school project, uvm, test bench building, OOT,
knowledage of pointer, makeflow, C Shell,
baiscly not hard question, all the answer can be google online.
and never got back from second round
Interview questions [1]
Question 1
There are block box modules, and you know nothing about what they are doing, behaior, output, input. Can you create a verification TB for it?
The overall process was smooth but complex, with multiple rounds of interviews, and things went great but got rejected without any reasoning. I felt that the interviews were going pretty smooth.
Interview questions [1]
Question 1
Designing a UVM checker from scratch for a made-up protocol
Accomplishing this task is certainly not a simple or effortless endeavor; it requires substantial effort, considerable time, and a dedicated, persistent approach, far from being straightforward or easily achievable at all.
ASIC Design Verification Engineer applicants have rated the interview process at Apple with 3.2 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 40% positive. To compare, the company-average is 64% positive. This is according to Glassdoor user ratings.
Common stages of the interview process at Apple as a ASIC Design Verification Engineer according to 5 Glassdoor interviews include:
Presentation: 33%
Group panel interview: 17%
Phone interview: 17%
Skills test: 17%
One on one interview: 17%
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