First I got an HR screen. I was contacted via Linkedin. Then I got the first tecnical interview with a team member and finally I got the team leader interview.
Interview questions [1]
Question 1
How the UVM sequencer and the sequence handshake happens
I interviewed at Capgemini (Belgrade, Central Serbia)
Interview
Apply to jobs via mail, in few weeks HR will contact you, than you have short meeting with HR and that is it for no experience guys. I accepted job, bcs it was my first job. No technical questions. It was before 3years
Interview questions [1]
Question 1
There was no tehnical interview for no experience engineer
I applied through a recruiter. The process took 4 weeks. I interviewed at Capgemini (Bengaluru) in Aug 2022
Interview
The whole selection and recruitment process took more than a month. It was seamless experience. First written test followed by Technical and HR round were done. Interview was full relevant to the electronics and VLSI domain.
Interview questions [1]
Question 1
1. Difference between inter assignment and intra assignment delay
2. Blocking and Non- blocking procedural block
3. How to design AND gate using MUX
4. Signals used in FIFO.
5. Do FIFO required address or not?
6. What do you understand by synchronous and asynchronous circuit.
7. How can we disable the randomisation ?
8. Why we use virtual interface in verification environment?
9. How to select and give in the particular testcase which were generated in generator block?
Design Verification Engineer applicants have rated the interview process at Capgemini with 1 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 100% positive. To compare, the company-average is 66.3% positive. This is according to Glassdoor user ratings.
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