VLSI Design Engineer applicants have rated the interview process at Intel Corporation with 3.5 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 100% positive. To compare, the company-average is 73% positive. This is according to Glassdoor user ratings.
Candidates applying for VLSI Design Engineer roles take an average of 14 days to get hired, when considering 2 user submitted interviews for this role. To compare, the hiring process at Intel Corporation overall takes an average of 23 days.
Common stages of the interview process at Intel Corporation as a VLSI Design Engineer according to 2 Glassdoor interviews include:
Background check: 33%
One on one interview: 33%
Phone interview: 33%
Here are the most commonly searched roles for interview reports -
techinal interveiw was good, but i couldnt answer the questions to the expected level .
it was a telephonic interveiw. the process was for two days . The first interveiw was more like about introducing myself and about my educational qualifications ,the second one was a technical interveiw.
Interview questions [1]
Question 1
difference between asynchronous and synchronous counter?
I applied through college or university. I interviewed at Intel Corporation (Bengaluru)
Interview
Applied through college. Only one technical interview. Mainly asked the basics of digital flipflops fsms and cmos logic. They asked to write the verilog codes. Another panel asked questions in fabrication too
Interview questions [1]
Question 1
D flip flop, Setup time, Hold time, Finite state machine, Pattern Generator verilog code
I applied through an employee referral. The process took 2 weeks. I interviewed at Intel Corporation (Fort Collins, CO) in Aug 2011
Interview
phone interview: very basic questions on inverter characteristics, capacitances in mosfet, pipeling and cache basics,set up time and hold time violations...pretty easy stuff..discussed about my resume..
Onsite Interview:I had 4 1:1 interview sessions, Mostly digital vlsi design stuff, some architecture basics,k-map,fsm,logic,RC circuits. They gave me a finfet and asked to analyse it. over all it was easy but didn't get the offer because of the hiring freeze..