ASIC Design Engineer applicants have rated the interview process at Marvell Technology with 3 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 43% positive. To compare, the company-average is 58.9% positive. This is according to Glassdoor user ratings.
Candidates applying for ASIC Design Engineer roles take an average of 17 days to get hired, when considering 45 user submitted interviews for this role. To compare, the hiring process at Marvell Technology overall takes an average of 20 days.
Common stages of the interview process at Marvell Technology as a ASIC Design Engineer according to 45 Glassdoor interviews include:
Phone interview: 35%
One on one interview: 24%
Skills test: 13%
Group panel interview: 9%
Background check: 6%
Presentation: 5%
IQ intelligence test: 4%
Personality test: 3%
Drug test: 1%
Here are the most commonly searched roles for interview reports -
I applied online. The process took 2 weeks. I interviewed at Marvell Technology
Interview
First round telephone interview: A design manage of their Datacom group called me to schedule a telephone interview next week.
Asked questions based on my resume, projects, especially circuit logic design, STA, dynamic structure
He is very polite, nice people.
I applied online. I interviewed at Marvell Technology
Interview
very good . interview is not much difficult
just brush up your knowledge. I think so its better to prepare in depth concepts. interview based on semi conductor. panel of the this company is very nyc.it was good experience to me. Thank you.
I applied through an employee referral. The process took 4 weeks. I interviewed at Marvell Technology (New York, NY) in Oct 2018
Interview
Got an interview via referral. After a month a recruiter contacted and scheduled a phone interview for primary screening. The 1st interview was basic check on my background. A second interview was scheduled in 2 weeks. I was given a number of topics to review. The questions were on timing analysis, fixing timing violations, CDC, and power optimization for ASIC. The interview went very well. The interviewer was very nice and said he is impressed with my solid preparation. Afterwards I was given a basic verilog coding problem, which I was supposed to email them. Then a day later they told me they will proceed with another candidate because they didn't like my answers regarding timing analysis- which contradicts what the interviewer told me. It seemed to me that they are just looking at candidates and wasting their time. At this point they are not really ready to hire for this position.
I applied online. I interviewed at Marvell Technology in May 2018
Interview
I use linkdin to get interviw opportunity. HR arrange interview time.I just joined first run. No response after interview. Manager and team member interview me.
I have no ideas for other process.
Interview questions [2]
Question 1
1.How to deal with multi-bit CDC
2.How to analysis timing for clock gating cell
3.Synthesis flow