ASIC Design Engineer applicants have rated the interview process at Qualcomm with 3.3 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 50% positive. To compare, the company-average is 62.4% positive. This is according to Glassdoor user ratings.
Candidates applying for ASIC Design Engineer roles take an average of 11 days to get hired, when considering 18 user submitted interviews for this role. To compare, the hiring process at Qualcomm overall takes an average of 22 days.
Common stages of the interview process at Qualcomm as a ASIC Design Engineer according to 18 Glassdoor interviews include:
Phone interview: 33%
One on one interview: 25%
Presentation: 17%
Group panel interview: 13%
Skills test: 4%
Other: 4%
IQ intelligence test: 4%
Here are the most commonly searched roles for interview reports -
Phone interview followed by onsite. Total process took about a month. Phone interview for 45 min. Onsite interview was lengthy with 6 different people for 1 hr each. Got the offer in 2 weeks after the onsite interview.
Interview questions [1]
Question 1
Questions on Flip-flops, tristate buffer, logic design
I had 6 rounds total. The first two were with senior directors who really drilled into my past projects and took time to walk me through the team's work and org structure — they seemed genuinely engaged.
Then I had three rounds with staff engineers. We covered some coding questions I wrote edge detection logic and an FSM, but I made a couple of mistakes on the first pass that I caught and corrected when the interviewers pointed them out. We also talked about DV concepts like reference models and how to build self-checking testbenches.
The final round was with a senior MTS from the Markham office, and it was pure behavioral no technical questions, just asking about my background and team fit.
2 stage interview with first interview to get to know the position and team. 2nd interview was ~1hr long with all technical questions. Write a counter, make a nand gate with muxes, name some cdc/lint violations.
Interview questions [1]
Question 1
Write verilog for a counter, make a nand gate with muxes
Had a phone interview first. Then was called for on site interview. Had 6 interviews. One of them was on software, One was on basic circuits (undergrad level), other were SRAM design.