I applied online. I interviewed at Xilinx (San Jose, CA) in Jan 2019
Interview
1 Telephonic Interview + Day long On-site Interview Process(4 TIs + HR)
Overall Topics to prepare:
Digital(Muxes, FFs, Timing Params, Synchronizers and Asyn FIFOs, Clock domain crossings)
Verilog Coding Basics (Case, if-else, Practical Design problems)
SV Basics(Tasks Process, Fork Join)
Comp Arch(Pipelining, Load store Arch)
Scripting(Python/ Perl/ Tcl anyone)
Interview questions [1]
Question 1
#Telephonic Round:
Simple digital, verilog, timing Qs (30mins)
#Onsite Interview:(45 mins each)
Round 1:
Simple Digital Qs, Verilog code (Case , if-else difference, Blocking-Nonblocking difference, Unintensional latch problem), Power reduction techniques(Clk Gating) + extended Qs on same topic
Previous work related Qs , Module's overall working
Round 2:
Verification basics like:
What is fork -Join?
Tasks and fns
Pass by value , Pass by Refn
Logic behind Linked list entry removal(How address pointer is changed)
Round 3:
Verilog code for shift left, shift right, parallel load functionality
Some logical puzzales
Digital concepts like basic gates using Mux, Gate Reduction etc.
Round 4
More on Power reduction
Setup and Hold time eqs and Violation removal techniques
Diffn betn: Glich and Jitter and skew
It was easy and people were very good. Didn't seem to be tedious. It took just one hour and few questions, and rest it was easy. It was easy and people were very good. Didn't seem to be tedious. It took just one hour and few questions, and rest it was easy.
I applied online. I interviewed at Xilinx in Mar 2021
Interview
Technical screen followed by panel .Took three weeks from start to get the offer. The experience was overall very good.They tested the logic design basics, system verilog skills and analytical ability.
I applied through college or university. The process took 1 day. I interviewed at Xilinx (Kharagpur, West Bengal) in Dec 2020
Interview
It was very smooth in campus placements. They asked me first about what xilinx does and then went MTech project and technical questions about STA, verilog, C programming, ASIC design flow etc.
Interview questions [1]
Question 1
What does xilinx do? and why are you interested in this company?
Design Engineer applicants have rated the interview process at Xilinx with 3.1 out of 5 (where 5 is the highest level of difficulty) and assessed their interview experience as 77% positive. To compare, the company-average is 63.2% positive. This is according to Glassdoor user ratings.
Candidates applying for Design Engineer roles take an average of 10 days to get hired, when considering 13 user submitted interviews for this role. To compare, the hiring process at Xilinx overall takes an average of 17 days.
Common stages of the interview process at Xilinx as a Design Engineer according to 13 Glassdoor interviews include:
Phone interview: 26%
One on one interview: 23%
Presentation: 11%
Skills test: 11%
Background check: 9%
Personality test: 6%
Group panel interview: 6%
IQ intelligence test: 6%
Drug test: 3%
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