What is the difference between == and === ? What is the use of reg in verilog?
Analog Design Engineer Interview Questions
789 analog design engineer interview questions shared by candidates
1. Basic questions around transistors - particularly large W/L ratio ones. 2. A couple of circuits with pmos and nmos in a current mirror configuration - I was asked what would be the node voltages as a function of input to one of the transistor's gate. 3. Layout/cross section of inverter and small signal model of MOSFET
You have a current mirror. How do you solve problems with offset?
What is the significance of Gain & phase margin
They asked all about my projects each and every details. They also asked about all the different experience with tools, designs, basics etc. You should be thorough with all the content in your resume.
Simple two stage Opamp design
why capacitor does not allow sudden change in current
What are your short-term and long-term objectives?
What would be the effect of adding ESD protection to an output driver.
what is the region for a simple invertor working in the flat region in IV characteristics graph.
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