Will the CMOS NAND gate speed up by increasing VDD?
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
tell me about uvm testbench top
How would you make Clock dividers?
Personality is the most important thing.
which metal layer used for power/clock
Write some verilog for a 3 to 1 arbiter, with a priority client and 2 clients in a round robin.
How to make an AND gate with only XOR gates
varies and based on JD
I felt the most difficult question was about different metal layers and their properties
Knowledge on OOPs concept. encapsulation and polymorphism. Function overload or overriding - Virtual, and non virtual function . Given a transmission of send and recv of a signal from 1 to 15 timeslots, find latency of signal from send to recv and determine and min and max latency . Probably looking for knowledge in counter and loops and logical thinking in the short span
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