Write verilog code for D ff.
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Describe the projects you have worked on.
write a code to extract input and outputs
c++ swap, pipeline
They checked your resume and asked the questions related to your classes.
1st round: asked basic verilog questions like difference between wires & regs, difference between if-statements and case statements. Asked about projects on resume. Asked a small project and how I should approach it. 2nd round: gave a problem and had to create FSM and verilog.
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
What is a fpga and what is a lookup table?
What is your Ph.D. research?
Write a Fibonacci number generator in Verilog, output a number in each cycle.
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