Logical design, physical design, perl, System verilog (UVM)
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Explain ASIC Design Flow
Using 3 registers and two two-bit full adders, how to count to 9 given that one clock cycle is only enough the delay of a full adder.
Write the equation for set-up time for the circuit described. Give the hold equation for the same
Design a state machine for sequence detection.
What is Setup and hold time
2. some binary arithmetic.
Moderate, no unexpected questions asked.
write a verilog code of moving average
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