write a code to extract input and outputs
Asic Engineer Interview Questions
1,319 asic engineer interview questions shared by candidates
c++ swap, pipeline
Basic computer architecture questions, pipeline concepts and hazards. FSM for a sequence detector. Fibonacci using recursion and linked list reversal. Some scripting question which i could not answer.
My previous experience, as well as a few mock examples related to verification and what my process would be
Mostly related to system verilog, verilog and in general Digital Logic.
They checked your resume and asked the questions related to your classes.
Scripting (bash/python), basic VCS and CI/CD
1st round: asked basic verilog questions like difference between wires & regs, difference between if-statements and case statements. Asked about projects on resume. Asked a small project and how I should approach it. 2nd round: gave a problem and had to create FSM and verilog.
Emerging technologies in the microchip industry
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
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