Asked to design a FSM
Asic Engineer Interview Questions
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All the interviewers are Indians and were really nice. I had a really good conversation each interview is about an hour. Everyone had a set of questions prepared and asking me to solve. 1. Full SV - fork join_none, virutal functions, $cast, static variable, Cache size - direct mapping, MESI FSM, constarints, parity check - post randomize 2. STA - hold violations, max freq, FIFO depth, metasibility 3. DUT - muti master muti slave bridge verification - draw the env and testcases, AXI signals 4. UVM - phases, AXI why not APB?, AXI lite vs. AXI 3.0, Driver code, coverage class and do cross coverage. 5. HR -> about team work, resources you used in a project, set back you faced. Explained most employee benefits, applying for H1B and green card, etc
How does a uvm_test launch? What's the difference between task and function calls in UVM How do you connect different components if you have multiple transactions to be sent from one to another.
what 's the steps of synthesis?
Questions on Flip-flops, tristate buffer, logic design
How to do numerous tasks and kill off 1 task if any finish. Then wait for all to finish.
Design a two input XOR gate use 1 MUX.
Mainly focused on Low power as I said I am interested in low power. Asked about timing analysis STA setup hold and synthesis. Some basic rtl design with verilog vhdl.Basic CMOS modeling NAND gate and NOR gate. IN HR round as i was fail in one of the subject was asking about that subject but as i performed well they consider that.
Write Code: Count the number of ones in a bitstring. (Allowed to use HDL logic e.g. bit[0]==1)
1 : What's a strength / weakness of yours? 2.a : draw a circuit that implements the XOR operation using NAND gates 2.b : implement some memory unit (flip flop) for the output of the circuit 2.c : make one of the inputs of this circuit the input of another flip flop and its output the input to the XOR function 2.c.i : I kind of unintentionally prompted a question from them when I asked if the flip flops should be operated by the same or separate clocks. They proceeded to ask me what would happen if it was the latter case. 2.d : discuss what timing constraints you would need to be aware of for this circuit to function 2.e : how would you make the circuit run faster? what if timing constraints weren't met? what you need to do then? 2.f : code this circuit in verilog
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