Basic Computer Architecture questions. How to extend a 5 stage pipeline to 6 stages. Effects of doing that etc. A few programming questions.
Cpu Design Engineer Interview Questions
85 cpu design engineer interview questions shared by candidates
Virtual memory and paging, details of reservation stations, load store ordering, cache org, role of design verif and how do you interact with them.
one-hot assignment in verilog
Explain how an out-of-order processor works? How do you implement register renaming? Difference between an architectural and physical register file
On-campus: Verilog code writing, simple hardware design question using muxes and counter that was approached from different levels of abstraction. Phone Interview: Entirely computer architecture questions, including cache coherency protocols, cache organizations
Out of order processor, importance ILP (and it's advantages), Digital design (realizing basic gates with a MUX)
What is a hardstuck bug you have encountered during a project?
Case in verilog
Questions were FSM , types Draw 10X11 sequence detector using mealy and more machine Verilog code for FSM Fifo FIFO depth calculation
Questions on caches and virtual memory.
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