Draw the circuit base on the coding provided
Design Verification Engineer Interview Questions
1,116 design verification engineer interview questions shared by candidates
Power of 2, asynchronized and synchronized reset
1. C++, OOP 2. python: dictionary, swap values 3. Systemverilog: fork join 4. delete repeated element in an array 5. FIFO depth 6. find SA0/SA1 amoung 128 wires in minimal steps
Given an array of N elements and an array of M elements, both sorted in ascending order, create an array C that combines A and B in ascending order.
Leetcode style coding problems (array and bit manipulation)
Can you talk about your past experiences?
General questions about C, pipelining, caching, hazards and more C.
Functional coverage vs. Code Coverage
What is an Agent? Passive vs. Active.
what is Synchronous reset and asynchronous reset?
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