The first round had questions based on signal processing, basics of system Verilog, and I was given a take-home coding task to write an RTL code to check if there is an increment, decrement by 1 bit and if not, print error; and verify the same using a class-based testbench.
C++, SystemVerilog basics
if I talk to your previous boss, what he/she/they gonna say about you?
1. Constraint random, assertions, UVM env 2. OOPS concept 3. Coverage, python scripting 4. Verilog and digital logic
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
How to design a UVM testbench for a given design. What all componets are needed etc. Corner cases to test out and efficient way to build environment
System Verilog Virtual functions
System Verilog ,UVM Basics, Questions on Resume. Assertions,Constraints. Memory Verification plan
Constraint for 8-bit opcode (SystemVerilog) ➤ Only one bit can be set in the 8-bit opcode (i.e., one-hot encoding). Matrix size based on opcode bit index ➤ Based on which bit is set in the 8-bit opcode, generate a square 2D array (e.g., if bit 4 is set, matrix is 4x4).
Constraint randomization based question linking to AXI and memory filling
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