Design a 5 bit self correcting ring counter using 4 flip flops ?
Digital Design Engineer Interview Questions
821 digital design engineer interview questions shared by candidates
Set up and hold timing question. SDC constraints problem Cross Clock domain discussion.
Timing based questions were little tricky
nMOS operation condition in a circuit.
draw the layout of Nand circuit
Building a 3-input nand with 2-input nand, and some verilog questions, SV questions quesitons
How would you design and on odd counter and sequencer using dflip flops and gates.
On-site: Write a C-code to change the endianness of a given 32-bit number.
STA Setup / Hold TDC
Intro and things worked on. Then he asked me deep about the project I was working on. Synchronous FIFO question. Wrote for 50 continuous cycle s in any 100 cycles but reading every alternate cycles. Depth reqd? How to design synch fifo ? How async fifo ? Is it possible to write and read from sync FIFO built using single port sram in same clock cycle ? Setup time and why we need it ? How will multiply by 63 ? Optimize way of finding the square of a number ? 1, 4, 9, 16, 25,
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