Basics of clock gating and virtual clocks
Physical Design Engineer Interview Questions
711 physical design engineer interview questions shared by candidates
Clock tree synthesis, STA
Tell me about yourself
Upf commands CTS and power relation Mscts advantages Low power techniques
they asked about my project, what all physical cells that I know, what is ICG and some aptitude questions
CMOS inverter layout and basic mos theory, STA problem for setup and hold , static and dynamic power reduction. All Interviewer are very helpful if you struck somewhere.
what is vlsi? fabrication process of cmos external biasing of cmos Transfer characteristics of CMOS Cmos logic gate with truth table what are sequential Flip flops truth table of flip flops timing diagram of d flip flop some basics about semiconductor and biasing process
given waveforms of D, clk, Q and out of multiplyng by 2 and shifting. I need to draw the FF system.
describe the APR flow. I did one project in school using APR in Cadence.so they asked me on that secondly they tested scripting skills, write a perl script to dump to manipulate few string s and pipe it to a csv file
What is On Chip Variation?
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