How do you handle traffic between 2 units using a FIFO?
Pre Sales Interview Questions
2,630 pre sales interview questions shared by candidates
Questions about past experience with Verilog and VHDL
Basic computer organization and digital logic questions
Name your strengths/weaknesses
How many question been asked in the interview
Basic SV/UVM questions
What is TLB cache? Why is it used?
use MUX 2->1 to implement XOR
In validation they asked stuffs I never been through.
Explain handshaking in USB3 Write a C program to reverse each word in a sentence and then reverse the sentence word by word. ex: he is a good boy -> yob doog a si eh. Linux Kernel Module programming for USB3 Memory organization related- segmentation fault, associative cache etc. DMA
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