What could be or could not be synthesized in Verilog/VHDL?
Principal Engineer Interview Questions
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What is your process and how do you think it fits in the existing process? (Paraphrased)
Time waster: Traverse a tree
Find the lowest number from the array.
You talk about tokenisation can you please explain what this is on your CV and Fintech?
You have SAFe on your CV, what does that mean?
Given a a roomba like vacuum with a limited APIs like turn left, turn right, go forward, clean, detect clean area, how would you ensure you have traversed and cleaned an entire room. Bonus: how would you optimize to save energy?
GTM, new product development/launch, market sizing and estimation etc.
Difference between variable & function hoisting?
Whats a class ?
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