virtual memory standard libraries in C how to build a cache how will you move data in cache what is recursion linked lists, binary tree, flat architecture, how a CPU would work
Verification Design Engineer Interview Questions
1,116 verification design engineer interview questions shared by candidates
Given an expression with brackets, Suggest a solution to check legality: Examples: ((), )(), (((} , {[()]
1. Basics of digital electronics like combinational gates, mux, flip flops, registers, finite state machines, Verliog/ RTL code. 2. Difference between i) setup and hold time, ii) synchronous and asynchronous rests(explain through verilog coding) , iii) mealy and moore iv) tasks and function v) combinational and sequential vi) blocking and non-blocking statements vii) inter and intra statement delay 3. Verilog code for flip flops and finite state machines. 4. Maximum operating frequency of the circuit which had a combo logic between 2 flip flops. (HINT: Setup and hold time equation's based ques) 5. Varying what factor in the equation of setup and hold time can the violation of setup and hold time can be eliminated. (HINT: By varying combo propagation time.) 6. Flip flop conversions, truth tables, a logic implementation through mux, kmaps. 7. ASIC flow diagram, what is netlist, what is RTL. 8. OOPS concepts, sorting algorithms, time complexity. 9. Types of interrupts, what happens when interrupt is called. 10. What is function, what is class. How a class is called. 11. Detecting a sequence through mealy and moore state machines.
My experience was bad in 2 rounds otherwise good in other 3 rounds.
I was given a direct coding question about how I would determine whether two patterns given to me were correct.
implement blackjack with classes in python
Then asks questions in SV & UVM starting from basic concepts to transaction level modelling & even asks you to develop a UVC for a protocol.
Not Applicable and confidential as per norms
Given read and write freq, how to calculate FIFO depth?
First Phone interview Computer Architecture stuff: OOO, memory dependencies, Piplelining, Fetch stage, Branch Prediction System Verilog: coverage and assertion writing Digital Logic: Implement AND and OR using 2:1 mux Asked to rate myself in C++, System Verilog Second Phone Interview: Similar Comp Architecture questions C program to sort array. Binary search vs Linear Search. Time complexity.
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