Few puzzles and Projects in my resume
Verification Design Engineer Interview Questions
1,116 verification design engineer interview questions shared by candidates
Teamwork that related to the position.
My previous experience, basic assertions and fifo programming
1. Difference between inter assignment and intra assignment delay 2. Blocking and Non- blocking procedural block 3. How to design AND gate using MUX 4. Signals used in FIFO. 5. Do FIFO required address or not? 6. What do you understand by synchronous and asynchronous circuit. 7. How can we disable the randomisation ? 8. Why we use virtual interface in verification environment? 9. How to select and give in the particular testcase which were generated in generator block?
Questions mostly about the project. Basics of Pcie protocol
What is the difference between task and function
Explain the structure of uvm verification environment.
Question about digital design and system verilog and uvm related questions
mux tree, FSM, Regions, NBA, DDR, Swapping of variables, crystal oscillator, full adder using 2x1 mux
functional coverage, types of bins, types of array, constraint examples, virtual class,threads
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