Constraint and assertion , gate level simulation
Verification Design Engineer Interview Questions
1,116 verification design engineer interview questions shared by candidates
Questions on interface, clocking blocks, assertions, uvm, X propagation.
Describe what a virtual function does?
Test cases for a 2 input, 2bit adder.
Difference between Nonblocking vs blocking assignments
Explain about FIFO, Clk generation, State machine
Verilog based questions - circuit was given and then i had to give an optimized code for it.
What is register renaming? How it works?
every details on uvm, some coding question and data structure
Explain caching and cache coherence
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