Basic digital, verilog questionscan be answered if you know the concepts well, Sv was totally into randomization , coverage and assertions. Uvm basic things initial rounds and in depth in last round. In manager round all digital, verilog, sv and uvm were covered
Draw MOSFET ID vs Vgs and Vds characteristics
Q: Design d-ff using Mux?
How to write assertion with frequency
Do you like to document things?
System Verilog and UVM based questions
What is the most challenging task you performed in your career so far ?
1. Write a Verilog code to generate a clock signal at a certain frequency. (a lot of Verilog basic problems) 2. draw a CMOS logic gate 3. Why do you want to be a DV person? 4. What is the most interesting class you took? 5. Other real-life related engineering problems (related to SNR)
Are you a team player?
There's a circuit diagram of a pulse generator: a 2-input NAND gate with one of the inputs three inverters downstream from the other input, with some propagation delay for each inverter. Given the timing diagram of the input, what does the output look like?
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