It was strange interview I ever had. It was a telephonic interview and he asked me to explain system verilog code for small program, he was writing program as I was explaining him and he expect program to compile and run. Its all telephonic. which is strange. I did not like it and also not selected for next round
Name all the ROB entries in Tomasulo
Design a queue in verilog.
How does an SRAM work?
UVM questions. SVA questions. UPF questions. Short path algorithm between A and B Sorting array algorithm Give you basic design and ask you for verification plan, how will you implement scoreboard , why that choice... Question about blocking/non blocking assignment
Self-assessment, technical skills and soft skills
FiFo depth, Assertions, FSM, Clocks
1. FSM to check if a number is divided by 5. 2. Implement basic logic gates using a MUX and NAND. 3. Reverse a linked list. 4. Questions about a FIFO
pipeline processor architecture, hazard, shared memory problem, cache issues—remote repeated words both in SystemVerilog. I answered how to do it in python, but he insisted Con using c or SystemVerilog. In the last question, he asked me why I choose design verification. The whole procedure lasts about 53 minutes, quite tense I would say. I did not answer the memory coherence and delete repeat words in C. I would say I did not do it well. Hoping this could help others to get job. Just preparing questions.
Memory allocation
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