Cache coherence, Pipelining, Pseudo code, FSMs
Verification Interview Questions
3,816 verification interview questions shared by candidates
It gets very technical ranging from Electrical fundamentals to RF fundamentals and then they start to dig deep on each aspect. Know your chip caps really well! I was asked questions on smith charts, imedance matching, typical RF receiver/transmitter systems, signal integrity issues, characteristics of RF amps. As far as behavioral questions were concerned - challenges faced in your last project, how did u solve it and what would your ex boss say about you if I asked him for a reference.
Questions related to pipelining, hazards, in-order processor, out of order processor, Register renaming, branch prediction, caches and virtual memory
Basic of sv uvm and current projects
System verilog,uvm,verilog constraints and assertions , about projects
Tell us a time that you faced a technical challenge and how you overcame it.
Basic UVM questions, advanced systemverilog
2.fsm design for counters
5.structre of a processor, pipelining, and cache coherence based questions
Lcm, Swap, Factorial for C coding Write constraints in system verilog
Viewing 1981 - 1990 interview questions