Build a verification environment to an ordering block.,what woukd be generation and coverage like.
Verification Interview Questions
3,814 verification interview questions shared by candidates
Basics of digital, verilog, system verilog and uvm.
tell about your previous projects
Given a function in C++, describe the intended purpose, what it returns, and fix the code so it actually returns what it is meant to return.
What are the types of assertions in System Verilog? What is a linked list?
Given this design and their features, explain how you would build a UVM testbench to verify it.
Design a full adder using MUX
What is a state machine?
Mesi Moore and mealy Coding
A router transmits the data. If the data is destined for same address then the packets should arrive in the same order as it is transmitted. The packet sent second is not allowed to overtake the one sent first. But if the packets are destined for different address it can overtake the other packet. How will you verify this design. The packet does not contain any ID.
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