Design an FSM for an elevator, different kinds of coverage, describe some RTL bugs you found in your current role, describe UVM testbench, how are sequences and drivers connected
Verification Interview Questions
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FIFO depth, and ASYNC FIFO test plan
pseudocode for factorial and think of cases that would fail it, they had given me a scenario and to assess it. A design was given and was asked to identify bugs in it.
como voce se ve daqui 19 anos
qustions asked in written test are based on the following topics 1.design of FSM 2. STA 3.design of some logic functions and reduction of logic functions face to face in interview are the questions given in the written test.
describe a project you worked on..
all technical questions about the projects on my resume
What hours where I looking for?
Questions like blocking assignment and non blocking assignment difference
Why do you want to work here? Questions about my technical ability and work ethic.
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