Technical Questions: Questions about Latch vs Flip-Flop. Draw a D-flip-Flop, linked them together to make a linear feedback shift register. Draw timing diagram. (Setup/Hold time). Draw complementary style inventor. (Pmos,Nmos). Why Pmos is on the top? talked about low power design principle. Problem solving: A problem about "Three boxes are labeled “Apples,” “Oranges,” and “Apples and Oranges.”". Google it. Write a program to find a parenthesis in a string. Ex: A(+SDF09)(u&(.
The first one was about implementing a NOT gate with MUX.
for phone interviews, basic data structure algorithms. 1. Reverse singly linked list. Onsite was more difficult with a bit of algorithms, computer architecture, design verification, and OOP.
How do you as a back-end designer work with front-end (RTL/Synthesis) designers to solve tough timing problems, for example, under what circumstances do you absolutely need them to solve on their side? What information or files do you provide to them?
Phone interviews : CMOS basics, usual some gate/logic using one gate, timing related questions, FIFO depth, max in array, palindrome Onsite : CDC - a lot on various techniques and improvements from one to another, clock MUX logic, Clock dividers, FSM , Timing related question based on designs above
Typical timing probs (fix hold time and setup time violations, power saving techniques, jitter, skew) Some simple comp arch (5 stage pipeline, hazards and how to fix them, VM) HM asked me to go through my projects in detail and describe logic synthesis on an FPGA, design an arbiter, list all timing fixes I knew and explain in detail.
- Questions on different types of cache - Difference b/w them - Explain inclusive and exclusive caches
Asked basic questions based on resume. The position required CPU architecture knowledge. I hadn't taken any of those courses, so interviewer asked only IC designing questoins.
describe the equations for setup time and hold time on a registered path with clock skew
whats the ad and disad of using large cache and small cache
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