What will happen if a default case is not used in a case statement?
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Check the awareness of applying pre and post randomization in variables in uvm_object.
5/6 interviewers asked about past work experience, design problems, and analysis of circuits. One interviewer asked general get-to-know you questions.
Also asked some C++
Design group people are very very nice. In verification group, was asked knowledge in undergraduate school, like communication principle and analog circuit questions. I almost forgot the communication principle, but he kept on asking.... I kind of hate this guy
It was mainly behavior questions about resume
Fifo functionality and verilog code to write
Describe one of the problems related to Dynamic logic and the solution to it
1: Asked me about my resume. Mainly about the DDR2 memory controller on my resume. 2: Asked me about FPGA.
About my understanding of layout tools, the environment and fluency on the design flow.
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